FIG. 1 illustrates a block diagram of a prior art memory device. The memory device 100 includes a memory cell array 110, a clock synchronizing circuit block 120, a read command path block 130, a data output buffer 140, a mode register 150 and a latency circuit 160. In operation, data is written into the memory cell array 110 and read out from the memory cell array 110. If a read command is asserted to the memory device 100, data is read out from the memory cell array 110 according to an externally received address. A buffer 116 receives and temporarily stores the address. A row decoder 112 receives the stored address and decodes a row address of the memory cell array 110 from the address. A column decoder 114 receives the stored address and decodes a column address of the memory cell array 110 from the address. The memory cell array 110 outputs the data addressed by the row and column addresses. The data output buffer 140 receives the data output from the memory cell array 110, and outputs the data based on a latency signal from the latency circuit 160 and an internal data output clock signal CLKDQ.
The clock synchronizing circuit block 120 generates the data output clock signal CLKDQ based on an external clock signal ECLK. The external clock signal ECLK serves as a reference clock signal for most commands of the memory device 100. Specifically, most commands are asserted to the memory device 100 in synchronization with the external clock signal ECLK. As shown in FIG. 1, the clock synchronizing circuit block 120 is a delay locked loop (DLL) circuit. The DLL circuit 120 includes a variable delay 122, a data output buffer replica 124 and a phase detector 126. The DLL circuit 120 is a well known circuit such as described in U.S. Pat. No. 5,614,855; and therefore, will not be described in detail. The DLL circuit 120 generates the data output clock signal CLKDQ as a phase lead version of the external clock ECLK. Namely, the data output clock signal CLKDQ has the same frequency as the external clock ECLK, but the pulses of the data output clock signal CLKDQ precede the pulses of the external clock signal ECLK by a data output time tSAC. The data output time is a measurement of the time it takes the data output buffer 140 to output data. Accordingly, the DLL circuit 120 causes data to be output from the data output buffer 140 in synchronization with the external clock ECLK.
The read command path block 130 receives the read command and the external clock signal ECLK. An internal clock generator 132 receives the external clock signal ECLK and generates an internal clock signal PCLK from the external clock signal ECLK. Specifically, the internal clock signal PCLK is a buffered version of the external clock signal ECLK. Therefore, the internal clock signal PCLK has the same frequency as the external clock signal ECLK and the level of the internal clock signal PCLK swing is a CMOS level (VSS-VCC) buffered signal delayed from the external clock signal ECLK. The internal clock signal PCLK is used to control peripheral circuits (not shown) such as data sense amplifiers, data multiplexers, etc., in the memory device 100. A read command buffer 134 in the read command path block 130 receives the read command and the internal clock signal PCLK. The read command buffer 134 inputs the read command synchronized with the internal clock signal PCLK, and outputs an internal read signal PREAD, which is supplied to the latency circuit 160.
The memory device 100 has several modes of operation. The mode register 150 stores a mode register set (MRS) command asserted to the memory device 100. The MRS command indicates the mode of the memory device 100. A CAS latency CLi (where i is a natural number) is determined by the MRS command. The CAS latency indicates the number of clock cycles of the external clock signal ECLK that should occur between the receipt of a read command or column address until data is output by the memory device 100. Stated another way, data is output from the memory device in a CAS latency number of clock cycles after receipt of the read command (a column address being asserted together with the read command).
The latency circuit 160 receives the CAS latency from the mode register 150 and generates a latency signal such that the data output buffer 140 is enabled to output the data according to the desired CAS latency. More specifically, the data output buffer 140 outputs the stored data in response to the data output clock signal CLKDQ while the latency signal is enabled.
FIG. 2 illustrates a prior art latency circuit 160. As shown, the latency circuit 160 includes first, second and third D-flip flops 215, 225 and 235 connected in cascade. Each D-flip flop receives the data output clock signal CLKDQ at its clock input. The internal read signal PREAD is supplied to the D input of the first D-flip flop 215. The internal read signal PREAD and Q output of each of the first-third D-flip flops 215, 225 and 235 are respectively connected to first-fourth switches 210, 220, 230 and 240. The first-fourth switches 210, 220, 230 and 240 are respectively controlled by a CAS latency CL1, CL2, CL3 and CL4, and the output of the first-fourth switches 210, 220, 230 and 240 serve as the latency signal. In operation, only one of the CAS latency modes will be logic high; therefore, only one of the first-fourth switches 210, 220, 230 and 240 will transfer a signal for output as the latency signal. For example, when the CAS latency is 1, CL1 is logic high and turns on first switch 210. At this time, CAS latencies CL2, CL3, and CL4 are logic low. The internal read signal is then transferred as the latency signal via the first switch 210. When the CAS latency is two (i.e., CL equals 2), then CL2 is logic high, while CL1, CL3 and CL4 are logic low. Thus, the internal read signal PREAD is transferred as the latency signal via the first D-flip flop 215 and the second switch 220. The first D-flip flop 215 is triggered by the data output clock signal CLKDQ and delays the internal read signal PREAD being output as the latency signal by about one clock cycle. The operation when the CAS latency is three or four is similar to that discussed above with respect to the CAS latency of two, and therefore will not be repeated for the sake of brevity. Additionally, it will be understood that CAS latencies greater than four could be handled by the addition of more D-flip flops and switches.
FIG. 3A illustrates a timing diagram of the read operation when the CAS latency is 1. At a clock cycle C0, a read command 310 is asserted, and an internal read signal PREAD is generated by the read command path block 130 after an internal delay time tREAD. The latency signal is then enabled in response to the internal read signal PREAD as discussed above with respect to FIG. 2. As further shown in FIG. 3A, the DLL circuit 120 generates the data output clock signal CLKDQ such that the rising edge of the data output clock signal CLKDQ precedes the rising edge of the external clock signal ECLK by a period of time tSAC, where the time period tSAC equals the delay between enabling data output from the data output buffer 140 and the actual output of data from the memory device 100. As further discussed above with respect to FIG. 1, the data output buffer 140 outputs data when triggered by the data output clock signal CLKDQ only when the latency signal is enabled. Because the CAS latency has been set to 1 in this example, the latency signal is enabled prior to receipt of the data output clock signal CLKDQ. As a result, data is output from the memory device 100 in synchronization with the first clock pulse C1 of the external clock signal ECLK following the clock pulse C0 of the external clock signal ECLK when the read command 310 was received. The time delays tREAD and tSAC are internal delays set according to current process technology. Minimizing these delays improves the timing margin as to when the latency signal must be enabled before receipt of the data output clock signal CLKDQ. As the frequency of operation increases (i.e., the frequency of the external clock signal ECLK increases), the period between clock pulses of the external clock signal ECLK decreases. This reduces the timing margin for supplying the latency signal. Consequently, above a certain operating frequency, the latency signal enables after the data output clock signal CLKDQ, and the data is no longer output at the desired CAS latency. This results in a data read operation failure.
FIG. 3B illustrates another example of where the operation frequency is low enough such that a proper data read operation takes place for a CAS latency of 2. However, FIG. 3C shows the operation of the memory device 100 during a high frequency operation, wherein a data read operation failure takes place. As shown in this example, tREAD plus tSAC is greater than the period tCC of the external clock signal ECLK such that the internal read signal PREAD is asserted after the rising edge of a pulse CDQ1 of the data output clock signal CLKDQ. The latency signal thus becomes enabled after a pulse CDQ4 of the data output clock signal CLKDQ for the desired CAS latency. In the example of FIG. 3C, the desired CAS latency is 4, and as is shown, data is output according to a CAS latency of 5 instead of a CAS latency of 4. As a result, a data read operation failure takes place.
The memory device according to the present invention includes a memory cell array from which data is read. Read data is stored in an output buffer, which outputs data based on a latency signal generated in accordance with the desired CAS latency of the memory device. The memory device includes a latency circuit that permits a desired CAS latency of the memory device to be achieved without read operation error even when the memory device is operating at high frequency.
More specifically, the latency circuit selectively associates a plurality of transfer signals with a plurality of sampling signals based on the desired CAS latency to create a desired timing relationship between the sampling signals and the associated transfer signals. Read information is stored by the latency circuit in accordance with at least one of the sampling signals. and the latency signal is generated based on the transfer signal associated with the sampling signal used in storing the read information.
The arrangement and methodology of the latency circuit in the present invention allows for pointing or identifying a point in time as to when the memory cell array of the memory device is being read, and for pointing or identifying a point in time when to generate the latency signal with respect to the first pointer. By establishing the relationship between the first and second pointers based on the desired CAS latency, a read operation according to the desired CAS latency is achieved.